Embodiments of the present invention relate to embedded instruments, and more particularly, to systems and methods for time-correlating data from different embedded instruments, which need not have a common reference.
As systems become more complex, there is a need to measure performance or functionality using built-in or embedded instruments, which are proximally located to application circuitry within the system. In addition, there is a need to be able to relate (or time-correlate) data that has been collected in different parts of the system to gain a deeper understanding of the overall system behavior. In many cases, different parts of the system have different local time references or clock domains, which are used to sample data relative to the local reference or clock domain.
A conventional solution to the problem of time-correlating or synchronizing data from different sources is to distribute a common (i.e., global) reference signal through a carefully managed network to the sampling locations. This common reference is sampled along-side the data and then is used to relate data collected in different parts of the system. This technique is non-optimal or impossible in some systems where it is difficult or impossible to distribute a carefully managed common reference timing signal. This is true for applications having embedded instrumentation, external instrumentation, as well as for applications in which different instrumentation is spread over different devices.
Quite often, a system may be entirely contained on a chip. The system may include different embedded instruments, which may use the same or different local time references. Because of the practicalities of chip design, designers often complete one block of the design and then move onto next, and would rather avoid going back and redistributing the carefully timed common reference signal to other parts of the chip, particularly if the common reference signal is only to be used in debugging chip functionality. Although building communication paths themselves between different parts of the system is not it itself a particularly large challenge, accounting for a carefully timed global reference signal is a significant challenge, which can be made even more difficult due to timing delays, and the like, which are inherent in circuitry and paths between different components of the system or external systems.
Power islands introduce a further impediment to the conventional approach. Power islands are power savings techniques used in application-specific integrated circuits (ASICs), where certain portions of the chip are periodically powered down. It is difficult or impossible to distribute a uniform, consistent, global clock reference when different portions of the chip can be powered down at different times.
Moreover, in some cases, designers will prototype a chip design or ASIC design by spreading different functional blocks across multiple field-programmable gate arrays (FPGAs). The same problem exists, although now it is complicated even further because the common timing reference would need to be distributed between multiple FPGAs, in addition to being distributed between multiple embedded instruments within the FPGAs. Similar complications occur when multiple separate devices, such as external test and measurement instruments, are included in the overall system.
Accordingly, a need remains for an apparatus, system, and method that removes the requirement of a common or global timing reference while still allowing the system to generate time-correlated views of data from disparate sources, with disparate clock references.
The foregoing and other features and advantages of the inventive concepts will become more readily apparent from the following detailed description of the example embodiments, which proceeds with reference to the accompanying drawings.